1. Field of the Invention
The present invention relates to a semiconductor device. For example, the present invention relates to a semiconductor memory that continuously reads out data in synchronism with a clock.
2. Description of the Related Art
Recently, even a nonvolatile semiconductor memory is required to perform high-speed data read (to be, referred to as burst access hereinafter) in synchronism with an externally supplied clock. Also, the frequency of a clock by which a nonvolatile semiconductor memory operates is rising. Accordingly, the data output rate of a nonvolatile semiconductor memory is inevitably increasing.
At the timing of the edge of a certain clock, a CPU fetches data output from a semiconductor memory in synchronism with the edge of a clock immediately preceding the certain clock. In this case, the data must be input to the CPU a predetermined period before the edge of the certain clock. This will be called “setup” hereinafter, and the period of setup will be called “setup time” hereinafter. Also, the data must be kept input to the CPU for a predetermined period from the edge of the certain clock. This will be called “hold” hereinafter, and the period of hold will be called “hold time” hereinafter. Accordingly, each data output period must be equal to or longer than the hold time, and equal to or smaller than the difference between the period of one cycle of the clock and the setup time (e.g., Jpn. Pat. Appln. KOKAI Publication Nos. 2005-078510 and 2002-149252).
As the operating frequency rises, however, the condition of the data output period becomes strict. For example, when the operating frequency is 108 MHz, the data output period is 2 (inclusive) to 7 (inclusive) ns, so the allowable range is only 5 ns. In addition, a semiconductor element changes its characteristics in accordance with the voltage or temperature. This makes it very difficult to match the data output period with defined conditions while taking account of the voltage and temperature.
Also, the condition of the data output period fluctuates in accordance with the operating frequency. Accordingly, if a semiconductor memory is designed to match a CPU that operates at a high frequency, this semiconductor memory may not match a CPU that operates at a low frequency. That is, the versatility of the semiconductor memory deteriorates.